1. Technical Field
The invention relates generally to memory array analysis, and more particularly, to a memory array repair where repair logic cannot operate at the same operating condition as the memory array.
2. Background Art
Testing and repair of memory arrays prior to release to a customer is a common practice during integrated circuit (IC) and/or memory array fabrication. For example, ICs oftentimes include embedded memory arrays such as an embedded dynamic random access memory (DRAM) array, which requires testing and repair. These embedded memory arrays are analyzed by the fabricator using a built-in-self-test (BIST) unit that is included on the IC or using separate, stand alone testing units.
One challenge during testing is addressing situations where the memory array can operate at an operating condition that the repair logic, used to evaluate and repair the embedded memory array, cannot achieve. Repair logic may be any system, such as a redundancy analyzer, used to capture memory cell failures and repair and/or replace memory cell assignments to ensure proper operation of the embedded memory. For example, one operating condition at which a memory array may operate and the repair logic may not be able to achieve is a higher speed. For example, a memory array may run at, for example, 500 MHz, while the repair logic may only be able to run at, for example, 100-200 MHz. In this case, when the test unit runs with the memory array configured for the higher speed, i.e., 500 MHz, it is impossible for the repair logic to repair all faults at the higher speed. Another operating condition at which a memory array may operate and the repair logic may not be able to achieve is a higher latency. For example, a discrete DRAM array may have different amounts of latency. For instance, a conventional discrete DRAM array may have a 20 ns latency, i.e., 50 MHz, which is allowed to be broken into 4 separate clocks of 5 ns each, so that the memory array operates at 200 MHz. That is, once testing is started, data can be acquired every 5 ns, just not from the same address. Repair logic, however, is typically not sophisticated enough to handle latency with 4 clocks. In this case, an address input to the DRAM array during testing will be read out in such a way that it is always off by some parameter, e.g., a number of addresses. That is, the data read out of the memory array by the repair logic is always late by 3-4 cycles such that the address that exists in the repair logic is continuously trailing the memory array. As a result, the repair logic places repair data in the wrong DRAM array address, and proper repair cannot be achieved.
The above-described situation is especially problematic where repair logic is embedded with the memory array because it is generally impracticable to provide repair logic that operates at all of the operating conditions, e.g., higher speed, lower latency, etc., that the memory array can achieve because it uses up too much valuable silicon space. It also should be understood that this situation occurs for all types of memory arrays, embedded or discrete, and for BIST units and stand alone test units.
There is a need in the art for a way to repair a memory array where the repair logic is incapable of operating at the same condition as the memory array.